In the field of integrated circuit (IC) yield analysis, it has become increasingly challenging to evaluate very rare failure events (i.e., rarely occurring failure events) when a more of process variability sources exist. Failure rates at “high-sigma” tails of a distribution (e.g., 6σ or higher) are important, as an array demands billions of life cycles, and because failure of even only a few cells could be catastrophic. For example, for a 1 Mb memory block, to achieve yield of 90%, each individual memory cell of the memory block may require a failure rate that is less than 1e-7. To ensure capture of an incredibly rare failure event at a simulation-based evaluation/validation stage, more than 1e9 standard Monte Carlo (MC) simulations may be required.